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fig 20. normalized on-resistance vs. temperature fig 18. typical output characteristics fig 17. typical output characteristics fig 19. typical transfer characteristics
 
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     fig 24. maximum safe operating area fig 22. typical gate charge vs. gate-to-source voltage fig 21. typical capacitance vs. drain-to-source voltage fig 23. typical source-drain diode forward voltage 29
  
       
 
 
 
 
fig 26a. switching time test circuit v ds 90% 10% v gs t d(on) t r t d(off) t f fig 26b. switching time waveforms v ds pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. + - v dd fig 27. maximum effective transient thermal impedance, junction-to-case fig 25. maximum drain current vs. case temperature  -
 
   
 
 
 
 
     q g q gs q gd v g charge d.u.t. v ds i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - 12 v fig 29b. gate charge test circuit fig 29a. basic gate charge waveform fig 28c. maximum avalanche energy vs. drain current fig 28b. unclamped inductive waveforms fig 28a. unclamped inductive test circuit t p v (br)dss i as r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v

  
       
 
 
 
 
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legend 1- drain 2- source 3- gate  ?-4n''.  &.4;; -4 '+4)+   ?-4n''.  &.4;; -4 '+4)+   ?-4n''.  &.4;; -4 '+4)+   ?-4n''.  &.4;; -4 '+4)+   ?-4n''.  &.4;; -4 '+4)+  *6(*(=10=(  = 2*0 0/0$$:2 02 #0*0#$ *=1=12 )02 =12" $*6(0=$* *  0#$ *:2*(=12  .m 7;  .m 7;  .m 7;  .m 7;  .m 7;


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